1. Field of the Invention
The present invention relates to a semiconductor device including a guard ring.
2. Description of the Related Art
There has been a known technique of providing a guard ring around a circuit region formed at the surface of a semiconductor substrate. FIG. 1 is a sectional view of such a conventional semiconductor device including a guard ring. As shown in FIG. 1, in the semiconductor device, circuit regions 102 and 103 are formed at the surface of a p type silicon substrate 101. The circuit region 102 has a circuit as a noise source such as a digital circuit. The circuit region 103 has a circuit liable to be affected by noise such as an analog circuit. The circuit region 102 is provided with a p+ diffusion region 102a, while the circuit region 103 is provided with a p+ diffusion region 103a. Note that in FIG. 1, the elements other than the p+ diffusion regions 102a and 103a in the circuit regions 102 and 103 are not shown.
A p+ diffusion region 104 is formed to surround the circuit region 103. The p+ diffusion region 104 is connected to a ground potential line and provided with a ground potential. In the region except for the p+ diffusion regions 102a, 103a, and 104 at the surface of the p type silicon substrate 101, an STI (Shallow Trench Isolation) region 105 is formed, and a p well 106 is provided under the STI region 105.
In such a conventional semiconductor device, the circuit in the circuit region 102 operates to create electrical noise, which becomes substrate noise 107 and propagates through the p type silicon substrate 101 and the p well 106. At the time, if the p+ diffusion region 104 is not provided, the substrate noise 107 comes into the circuit region 103 and adversely affects the operation of the circuit in the circuit region 103. However, the p+ diffusion region 104 is formed between the circuit regions 102 and 103, and the p+ diffusion region 104 is provided with the ground potential, so that the substrate noise 107 is partly absorbed into the ground potential line through the p+ diffusion region 104. In this way, the adverse effect upon the operation of the circuit in the circuit region 103 can be prevented to some extent.
Furthermore, according to the technique disclosed by Japanese Patent Laid-Open Publication No. 2000-49286, a guard ring made of an n type diffusion layer is formed at the surface of a semiconductor substrate and a p type diffusion layer is provided in the n-diffusion layer, the n type diffusion layer is connected to a positive power supply terminal, and the p type diffusion layer is connected to a negative power supply terminal. According to the disclosure of Japanese Patent Laid-Open Publication No. 2000-49286, this allows the n type diffusion layer and the p type diffusion layer to be reversely biased to form a bypass capacitor, and the effect of the power supply noise upon the operation of the circuit can be prevented.
The disclosed technique as shown in FIG. 1 however still suffers from the following disadvantage. The ground potential line connected to the p+ diffusion region 104 forming the guard ring and the ground potential line (not shown) connected to the circuit region 103 having the affected circuit are provided as a common line, the substrate noise output from the circuit region 102 and absorbed to the ground potential line through the p+ diffusion region 104 changes the ground potential applied to a circuit in the circuit region 103 and adversely affects the operation of the circuit.
When the ground potential line connected to the p+ diffusion region 104 and the ground potential line (not shown) connected to the circuit region 102 having the noise source circuit are provided as a common line, the noise output from the circuit region 102 is transmitted to the p+ diffusion region 104 through the ground potential line and then comes into the circuit region 103 as substrate noise from the p+ diffusion region 104. In this way, by the above-described conventional technique, the substrate noise is not sufficiently shielded. In the disclosure of Japanese Patent Laid-Open Publication No. 2000-49286, the guard ring is connected to the power supply terminal, and therefore the same disadvantage is encountered.
Meanwhile, in the disclosure of Japanese Patent Laid-Open Publication No. 2002-16227, the guard ring is connected to an external power supply through a bonding pad and a reference potential is applied to the guard ring from the external power supply. According to the technique, the potential of the guard ring can be set independently of the affected circuit and the noise source circuit, and therefore the above-described disadvantage is not encountered.
The above-described technique however suffers from the following different disadvantage. In the semiconductor device as disclosed by Japanese Patent Laid-Open Publication No. 2002-16227, a dedicated bonding pad and a dedicated bonding wire must be provided in order to connect the guard ring to the external power supply, which increases the manufacturing cost for the semiconductor device. Note that the guard ring could be connected to an external power supply through a pin, but then the number of pins necessary for the semiconductor device increases, which also increases the cost. If the ground potential line connected to the guard ring is provided independently of the ground potential line connected to the circuits surrounding the guard ring, the manner of running the line in the semiconductor device would be complicated, which restricts the layout design. Furthermore, according to the technique of applying the ground potential to the guard ring, parasitic impedance is generated between the guard ring and the ground potential line, and the effect of absorbing the substrate noise is reduced. In the disclosure of Japanese Patent Laid-Open Publication No. 2002-16227, the guard ring is connected to the external power supply through the bonding pad and the bonding wire, and therefore impedance additionally provided to the guard ring is extremely large.